The present invention relates generally to an improved Bi.CMOS DRAM, and, more particularly, to particular arrangements including resistance means, a logical circuit, an input circuit, a fuse cutting circuit, a drive circuit, a power circuit, an electrostatic protection circuit, a semiconductor memory device including the foregoing components, a layout structure, and a testing method of the same, which are especially effective (although not limited) if applied to such a Bi.CMOS dynamic RAM which includes a memory array composed basically of dynamic memory cells and a peripheral circuit composed basically of a Bi.CMOS logical gate circuit.
Static RAMs are known which include a memory array, in which are arranged in a lattice form static memory cells composed basically of MOSFETs (i.e., Metal Oxide Semiconductor Field Effect Transistor, which is intended in this specification to cover all types of insulated gate transistors), and a peripheral circuit, which is composed basically of a Bi.CMOS logical gate circuit having a bipolar transistor and a CMOS logical gate circuit (i.e., Complementary MOSFET) in combination.
Such a Bi.CMOS static RAM is disclosed on pages 199 to 217 of "Nikkei Electronics" issued on Mar. 10, 1986, by Nikkei Mc-Graw Hill.
In the Bi.CMOS static RAM thus previously disclosed, it is intended to increase the degree of integration and reduce the power consumption by constructing the memory array of static memory cells, and it is also intended to speed up the operations by constructing the peripheral circuit of the Bi.CMOS logical gate circuit. Since, however, the static memory cell requires at least four MOSFETs, the increase in the high integration and capacity of the Bi.CMOS static RAM is restricted of itself. Therefore, we have developed the so-called Bi.CMOS dynamic RAM which comprises: a memory array composed of dynamic memory cells to be integrated more highly; and a peripheral circuit composed basically of the Bi.CMOS logical gate circuit. However, the mere application of the structure of the peripheral circuit such as the selections of the dynamic RAM or the peripheral circuit of the Bi.CMOS static RAM of the prior art to the Bi.CMOS logical gate circuit will not always provide an optimum solution, thus causing a problem that various performance characteristics of the Bi.CMOS dynamic RAM cannot be sufficiently enhanced.